[en]1.I was born in 1980 and graduated in 2002 Ming Northern Engineering, majoring in electrical engineering.[/en][cn]1.我出生于1980年，2002年畢業(yè)嗚北方工程學(xué)院，主修電子工程。[/cn] [en]2.I would like to apply for your newspaper published in the twenty-first century on the job advertisement.[/en][cn]2.我想申請(qǐng)貴公司刊登在二十一世紀(jì)報(bào)招聘廣告上的職位。[/cn] [en]3.I do BROWM company technician has been a year's time.[/en][cn]3.我在BROWM公司做技術(shù)員已經(jīng)有一年的時(shí)間了。[/cn] [en]4.As figure illustrates,a contemporary computer system consists of a central processing unit(CPU),pritnary storage, input devices,output devices,secondary storage and communications devices.[/en][cn]4.如圖所示，一個(gè)近代計(jì)算機(jī)系統(tǒng)包括一個(gè)中央處理單元CPU,主存儲(chǔ)器，輸入設(shè)備，輸出設(shè)備，副存儲(chǔ)器和通訊設(shè)備。[/cn] [en]5.The use of vacuum tube declined rapidly when a semiconductor device was invented that could per form many of the functions previously associated with vacuum tubes. [/en][cn]5.發(fā)明了半導(dǎo)體器件后,真空二極管的使用呈迅速下降趨勢(shì),因?yàn)榘雽?dǎo)體器件具有真空管的許多功能. [/cn] [en]6.Silicon transistors began to replace germanium transistors in the late 1950s, which made possible the next revolutionary step in electronics.[/en][cn]6.硅晶體管于20世紀(jì)50年代末代替了鍺工程學(xué)院，主修電子工程晶體管,它為電子學(xué)帶來(lái)了又一次的革命性進(jìn)步. [/cn]

用以實(shí)現(xiàn)任何設(shè)計(jì)的通用微處理器的話(huà)，電子行業(yè)就不會(huì)競(jìng)爭(zhēng)得如此激烈了。[/cn] [en]6.One way of creating fusion here on earth is to heat and compress pellets containing hydrogen to the temperatures and pressures needed to fuse the nuclei

[en]1.The commercial success of the integrated circuit industry was based on standard products representing digital logic families.[/en][cn]1.集成電路工業(yè)的商業(yè)成就是在以數(shù)字邏輯家族為代表的標(biāo)準(zhǔn)產(chǎn)品的基礎(chǔ)上取得成功的。[/cn] [en]2.This curriculum includes the elementary theory of passive component (resistor,capacitor and inductor

要被設(shè)計(jì)（當(dāng)然，盡管要用到一些庫(kù)）。[/cn] [en]2.For many years, however, it has been possible to build semi-custom integrated circuits using gate arrays. A gate array, as its name suggests, is an integrated circuit on which an array of gates has been created. The design of an application-specific integrated circuit (ASIC) using a gate array therefore involves the definition of how the gates in the array should be connected.[/en][cn]2.但是，多年以來(lái)，可以使用門(mén)陣列構(gòu)建半導(dǎo)體集成電路。門(mén)陣列，正如其名，是由許多邏輯門(mén)所構(gòu)建的集成電路。因此，使用門(mén)陣列進(jìn)行專(zhuān)用集成電路的設(shè)計(jì)包括定義列陣中的邏輯門(mén)是如何連接的。[/cn] [en]3.In practical terms, this means that one or two layers of metal interconnect must be designed. Since an integrated circuit requires seven or more processing stages, all the processing steps other than the final metalization can be completed in advance. Because the uncommitted gate arrays can be produced in volume, the cost of each device is relatively small.[/en][cn]3.在實(shí)際情況中，這意味著一到兩層的金屬互連必須被設(shè)計(jì)。由于集成電路需要七個(gè)或更多的加工過(guò)程，除了最終的金屬化，其它步驟都可以預(yù)先完成。因?yàn)檫@些未知用途門(mén)列陣可以大量生產(chǎn)，每個(gè)器件的成本非常低。[/cn] [en]4.A diode is reverse biased when the diode negative electrode voltage is higher than the anode electric potential. The diode internal resistance was extremely high by now.[/en][cn]4.當(dāng)二極管的正極電壓高于負(fù)極電位時(shí)稱(chēng)二極管反向偏置，這時(shí)二極管的內(nèi)部電阻非常高，所以一個(gè)理想的二極管可以阻擋反向的電流而讓正向的電流通過(guò)。[/cn] [en]5.There are four basic tests required for transistors in practical applications: gain, leakage, breakdown, and switching time. All of these tests are best made with commercial testers or oscilloscopes.[/en][cn]5.在實(shí)際應(yīng)用中，對(duì)晶體管須進(jìn)行四項(xiàng)基本測(cè)試：增益、漏電流、擊穿電壓和開(kāi)關(guān)時(shí)間。所有這些測(cè)試最好用通用晶體管測(cè)試儀和示波器進(jìn)行測(cè)試。[/cn]

收到的信號(hào)極其微弱，其電平僅比噪聲稍高一點(diǎn)。[/cn] [en]4.However,for applications in which the end product must process answers in real time,or must do so while powered by consumer batteries,GPPs comparatively poor real time performance and high power consumption all but rules them out.[/en][cn]4.然而，在最終產(chǎn)品必須實(shí)時(shí)響應(yīng)的應(yīng)用中，或者必

[en]1.Consider what we know intuitively about an integrator. If you apply a DC signal at the input (i.e. , zero frequency), the output will describe a linear ramp that grows in amplitude until limited by the power supplies. Ignoring that limitation, the response of an integrator at zero frequency is infinite, which means that it has a pole at zero frequency. (A pole exists at any frequency for which the transfer function’s value becomes infinite.)[/en][cn]1.我們?cè)趺磸闹庇^上理解積分器呢？假設(shè)在輸入端加上一個(gè)直流信號(hào)（頻率為0），那么在輸出端將會(huì)出現(xiàn)一個(gè)線性斜坡信號(hào),其幅度一直增至電源電壓。如果不考慮電源電壓對(duì)輸出信號(hào)的限制，積分器在零頻率上的響應(yīng)將是無(wú)窮大，這意味著它在零頻率點(diǎn)上存在一個(gè)極點(diǎn)（在任何使傳遞函數(shù)為無(wú)窮大值的頻率點(diǎn)上都存在一個(gè)極點(diǎn)）。[/cn] [en]2.While the complex frequency’s imaginary part helps describe a response to AC signals, the real part helps describe a circuit’s transient response. [/en][cn]2.復(fù)頻率的虛部有助于描述電路對(duì)交流信號(hào)的響應(yīng)，而其實(shí)部有助于描述電路的瞬態(tài)響應(yīng)。[/cn] [en]3.The low-pass filter’s transient response is more stable, because its pole is in the negative-real half of the complex plane.[/en][cn]3.低通濾波器的瞬態(tài)響應(yīng)更加穩(wěn)定，因?yàn)槠錁O點(diǎn)位于復(fù)平

for removal), one or more leads should be disconnected and care taken to avoid current paths in neighboring components when testing.[/en][cn]5.理想的方法是把該元件從線路中完整取出。但如果不方便的話(huà)（至少要在判別需要去掉之前），應(yīng)該斷開(kāi)一根或幾根引線，應(yīng)當(dāng)避免在測(cè)試時(shí)鄰近的元件之間有電流通路。[/cn]

在英語(yǔ)寫(xiě)作中，豐富的詞匯積累是提高表達(dá)能力和寫(xiě)作水平的關(guān)鍵。本文將深入探討如何通過(guò)詞匯積累的方式，提升英語(yǔ)作文的質(zhì)量和深度，讓文字更加生動(dòng)、精彩。 一、多元化的詞匯來(lái)源 閱讀廣泛：閱讀不同類(lèi)型的英文文獻(xiàn)，如小說(shuō)、報(bào)紙、雜志、學(xué)術(shù)文章等，可以擴(kuò)大詞匯量和理解范圍。通過(guò)閱讀，了解詞匯在不同語(yǔ)境中的使用方式，提高詞匯的運(yùn)用能力。 背誦經(jīng)典作品：背誦英語(yǔ)經(jīng)典作品中的優(yōu)美表達(dá)和詞匯，可以有效積累高質(zhì)量的用詞和句型，提升自己的寫(xiě)作水平。經(jīng)典作品中的精彩詞匯常常能夠激發(fā)靈感，為自己的作品帶來(lái)更多亮點(diǎn)。 二、系統(tǒng)化的詞匯整理與記憶 建立詞匯表：根據(jù)不同主題或語(yǔ)境，建立專(zhuān)門(mén)的詞匯表，包括常用詞匯、同義詞

有時(shí)也被稱(chēng)為可靠性因子。[/cn] [en]3.Why is skew important? In high-speed systems, clock skew forms an important component of timing margin. A skew of 1 ns is a significant portion of a 15-ns cycle time. If the timing budget does not allow for skew, it is highly likely that the system will perform unreliably.[/en][cn]3.為什么偏移這么重要？在高速系統(tǒng)中，時(shí)鐘偏移是時(shí)序富裕量的重要組成部分。在一個(gè)以15納秒為周期的時(shí)間里，1納秒的偏移都是很顯著的部分。如果時(shí)序預(yù)算不允許偏移，系統(tǒng)很可能無(wú)法穩(wěn)定運(yùn)行。[/cn] [en]4.In today's designs, with clock rates over 100 MHz and rise times commonly 1 nanosecond (ns) or less, designers cannot ignore the role interconnections play in a logic design. [/en][cn]4.在當(dāng)今的設(shè)計(jì)中，時(shí)鐘速率都超電阻與電源并聯(lián)連接,則電阻限定流入裝置的電流.電過(guò)了100MHz，并且上升沿通常只有1納秒或者更少，設(shè)計(jì)者不能忽視在邏輯設(shè)計(jì)中互連的重要性。[/cn] [en]5.The faster clock rates and rise times increase both capacitive and inductive coupling effects, which makes cross talk problems greater. They also mean shorter time for reflections to decay before the data is clocked and read, which decreases the maximum line length that can be used for unterminated systems.[/en][cn]5.更快的時(shí)鐘速率和上升沿都將增加電容耦合及電感耦合效應(yīng)，這使得串?dāng)_問(wèn)題更加嚴(yán)重。這也意味著在數(shù)據(jù)被寫(xiě)入和讀取之前的反射衰減時(shí)間更短，它減少了無(wú)終端系統(tǒng)中最大的可用線路長(zhǎng)度。[/cn]

電容器的絕緣電阻，假設(shè)電